Hardware Isolated Secure Processing System Within A Secure Element
AssigneeBroadcom Corporation
InventorsMark BUER, Theodore Trost, Jacob Mendel
Life of this patent
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Abstract
Systems and methods are provided that allow a secure processing system (SPS) to be implemented as a hard macro, thereby isolating the SPS from a peripheral processing system (PPS). The SPS and the PPS, combination, may form a secure element that can be used in conjunction with a host device and a connectivity device to allow the host device to engage in secure transactions, such as mobile payment over a near field communications (NFC) connection. As a result of the SPS being implemented as a hard macro isolated from the PPS, the SPS may be certified once, and re-used in other host devices without necessitating re-certification.
Claims21
A secure processing system, comprising:
- a secure processor;
- a memory block operatively connected to the secure processor for storing secure data, storing target of evaluation (TOE) security functions data, and providing a platform on which secure application software is loaded;
- a serial peripheral interface for communicating with a dedicated external flash memory unit;
- and
- an isolation bridge for communicating with external devices, wherein utilization of the isolation bridge effectuates a target of evaluation (TOE) boundary isolating the secure processing system from the external devices.
A system, comprising:
- a host device comprising a host processor and a first flash memory unit;
- a secure processing sub-system for at least one of storing secure data, storing target of evaluation (TOE) security functions data, and providing a platform on which secure application software is loaded, the secure processing sub-system comprising an isolation bridge and implemented as a hard macro;
- a peripheral processing sub-system for relaying communications to and from the secure processing sub-system and the host device, wherein the secure processing sub-system is hardware isolated from the peripheral processing sub-system;
- a connectivity device for providing communication capabilities for the host device;
- and
- a plurality of interfaces comprising:
- at least one physical transport slave interface within the peripheral processing subsystem for the relaying of the communications to and from the secure processing sub-system and the host processor;
- one of a single wire protocol (SWP) or a dual wire protocol (DWP) interface for accessing the first flash memory unit;
- and
- at least a physical transport master interface within the secure processing subsystem for accessing a second flash memory unit dedicated to the secure processing sub-system.
Dependencies are inferred from the claim text.