Digital circuit design method and associated computer program product

A computer program product for performing a digital circuit design, when a program of the computer program product is executed by a computer, comprising:

• before performing a physical design:
• a first program instruction, for performing logic synthesis according to a Register Transfer Level (RTL) design and a plurality of constraints to at least generate a netlist, a standard delay format file and a first constraints file;
• a second program instruction, for retrieving information of at least a specific node of circuit from the first constraint file to generate a second constraint file;
• a third program instruction, for generating an updated standard delay format file according to at least the standard delay format file and the second constraint file, wherein a delay of the specific node of the updated standard delay format file is less than a delay of the specific node of the standard delay format file;
• and
• a fourth program instruction, for using the netlist and the updated standard delay format file to perform a pre-post-layout simulation.

A digital circuit design method, comprising:

• before performing a physical design:
• performing a logic synthesis according to a Register Transfer Level (RTL) design and a plurality of constraints to at least generate a netlist, a first standard delay format file and a second standard delay format file, wherein regarding at least a specific node of a circuit, a delay of the specific node in the second standard delay format file is less than a delay of the specific node in the first standard delay format file;
• and
• using the netlist and the second standard delay format file to perform a pre-post-layout simulation.