Apparatus and method for deadlock avoidance
AssigneeCray Inc.
InventorsEdwin L. Froese, Eric P. Lundberg, Igor Gorodetsky, Howard Pritchard, Charles Giefer, Robert L. Alverson, Duncan Roweth
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AssigneeCray Inc.
InventorsEdwin L. Froese, Eric P. Lundberg, Igor Gorodetsky, Howard Pritchard, Charles Giefer, Robert L. Alverson, Duncan Roweth
Estimating the term…
An improved method for the prevention of deadlock in a massively parallel processor (MPP) system wherein, prior to a process sending messages to another process running on a remote processor, the process allocates space in a deadlock-avoidance FIFO. The allocated space provides a “landing zone” for requests that the software process (the application software) will subsequently issue using a remote-memory-access function. In some embodiments, the deadlock-avoidance (DLA) function provides two different deadlock-avoidance schemes: controlled discard and persistent reservation. In some embodiments, the software process determines which scheme will be used at the time the space is allocated.
A computer-implemented method for deadlock avoidance in a parallel-processor system, wherein the parallel-processor system includes a plurality of network nodes, wherein each one of the plurality of network nodes includes a node buffer, a processor and local memory, and a deadlock-avoidance (DLA) engine, wherein the plurality of network nodes includes a first network node having a first node buffer, a second network node having a second node buffer, and a third network node having a third node buffer, wherein each one of the plurality of network nodes is operatively coupled to a plurality of other network nodes over a network, and wherein at least one software process executes on the respective processor of each one of the plurality of network nodes, the method comprising:
A non-transitory computer-readable medium having instructions stored thereon for causing a suitably programmed information processor to perform a deadlock-avoidance method in a parallel-processor system,
A parallel-processor system comprising:
Dependencies are inferred from the claim text.