Variable frame length virtual gpio with a modified uart interface
AssigneeQUALCOMM Incorporated
InventorsLalan Jee Mishra, Richard Dominic Wietfeldt, James Lionel Panian, Radu Pitigoi-Aron
Life of this patent
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Abstract
A virtual GPIO interface is provided that receives a transmit set of GPIO signals from a processor. The virtual GPIO interface transmits a portion of the transmit set of GPIO signals over GPIO pins in a conventional fashion. However, the virtual GPIO interface provides a remaining portion of the transmit set of GPIO signals to a finite state machine that serializes the GPIO signals in the remaining portion into frames of virtual GPIO signals. A modified UART interface transmits the frames over a UART transmit pin responsive to cycles of a UART oversampling clock.
Claims22
An integrated circuit, comprising:
- a first processor;
- a plurality of GPIO pins;
- a virtual GPIO interface configured to receive a transmit set of GPIO signals from the processor and to transmit a first portion of the transmit set over the GPIO pins to a remote second processor;
- a finite state machine configured to serialize a remaining second portion of the transmit set of GPIO signals from the virtual GPIO interface into at least one first frame of virtual GPIO signals;
- and
- a modified Universal Asynchronous Receiver/Transmitter (UART) interface configured to transmit the at least one first frame to the remote second processor over a UART transmit pin responsive to cycles of an oversampling clock.
A method, comprising:
- receiving a transmit set of GPIO signals at a virtual GPIO interface from a first processor;
- transmitting a first portion of the transmit set of GPIO signals through dedicated GPIO pins to a remote second processor;
- serializing a remaining second portion of the transmit set of GPIO signals into at least one first frame of virtual GPIO signals;
- and
- transmitting the at least one first frame of virtual GPIO signals over a UART transmit pin to the remote second processor responsive to cycles of an oversampling clock for a modified UART interface.
An integrated circuit, comprising:
- a first processor;
- a plurality of GPIO pins;
- a virtual GPIO interface configured to receive a transmit set of GPIO signals from the first processor and to transmit a first portion of the transmit set over the GPIO pins to a remote second processor,
- a finite state machine configured to serialize a remaining second portion of the transmit set of GPIO signals from the virtual GPIO interface into at least one first frame of virtual GPIO signals;
- and
- means for transmitting the at least one first frame over a single transmit pin to the remote second processor responsive to cycles of an oversampling clock.
Dependencies are inferred from the claim text.