Bus interface circuit

A bus interface circuit for each of a plurality of slave devices, each connected to a data channel and a clock channel supplied from a master device, the bus interface circuit comprising:

• a head information detection circuit that detects head information supplied on the data channel and indicates the head of a data transfer, the head information circuit generating a first signal when the head information is detected;
• a clock control circuit that receives the first signal from the head information detection circuit and in response generates an internal clock that is synchronous with a clock on the clock channel, and that stops generation of the internal clock in response to receipt of a second signal;
• and
• a data analyzing circuit that includes a destination detection circuit that includes destination information that identifies each bus interface circuit, wherein
• the destination detection circuit detects whether destination data provided on the data channel and synchronous to the internal clock matches the destination information identifying a bus interface circuit and the destination circuit providing the second signal to the clock control circuit to stop the internal clock when the destination information does not match.

A method for operating a bus interface disposed in each of a plurality of slave devices to which a common data channel and a clock channel are supplied from a master device, the method comprising:

• detecting head information on the data channel and indicating the detected head information with a first signal;
• starting an internal clock synchronous to the clock on the clock channel in response to the first signal;
• capturing destination information on the data channel synchronously with the internal clock;
• comparing the captured destination with internal destination information identifying one of the bus interfaces of the slave devices to determine whether or not there is a match;
• if there is a match for one of the bus interfaces, maintaining the internal clock and capturing data from the data channel synchronously with the internal clock in the bus interface;
• and
• if there is not a match for one of the bus interfaces, stopping the internal clock in the bus interface and preventing the capture of data from the data channel.