System and Method for Sharing a Solid-State Non-Volatile Memory Resource
AssigneeQUALCOMM Incorporated
InventorsNHON TOAI QUACH, YANRU LI, WILLIAM EDWARD KIMBERLY
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Abstract
A computing device and methods for exposing a solid-state non-volatile memory element to multiple masters in a computing device are disclosed. A portion of a solid-state non-volatile memory element includes code and data for use by a non-boot processing resource. A host controller in communication with the solid-state non-volatile memory element is modified to receive and respond to a resource identifier unique to the processing resource that is requesting read access to the solid-state non-volatile memory element. Logic executed by a boot master and logic executed by a non-boot processing resource are synchronized in response to a set of indicators.
Claims30
A method for exposing a solid-state non-volatile memory element to multiple masters in a computing device, the method comprising:
- identifying a boot master in communication with a first memory element;
- identifying content useful to a non-boot processing resource;
- storing the content useful to the non-boot processing resource in a solid-state non-volatile memory element coupled to the computing device;
- generating a set of indicators responsive to a first operational condition of the solid-state non-volatile memory element and further responsive to a second operational condition of the non-boot processing resource;
- and
- conditionally executing logic with the non-boot processing resource to expose the content useful to the non-boot processing resource or executing logic with the boot master to expose content other than the content useful to the non-boot processing resource from the solid-state non-volatile memory element.
A computing device, comprising:
- a system-on-chip including a boot master and a non-boot processing resource;
- an interface bus in communication with the boot master and the non-boot processing resource;
- a memory controller coupled to the interface bus and to a random access memory element, wherein the boot master is configured to allocate storage in the random access memory element for a set of indicators;
- and
- a host controller coupled to the interface bus and to a solid-state non-volatile memory element, the solid-state non-volatile memory element having stored therein code and data dedicated for execution and use by the non-boot processing resource, the set of indicators responsive to a first operational condition of the solid-state non-volatile memory element as identified by the host controller and further responsive to a second operational condition of the non-boot processing resource,
- wherein the system on chip conditionally executes logic with the non-boot processing resource to expose the code and data dedicated for execution and use by the non-boot processing resource or executes logic with the boot master to expose content other than the code and data dedicated for execution and use by the non-boot processing resource from the solid-state non-volatile memory element.
A computing device, comprising:
- means for controlling data transfers to and read access from a solid-state non-volatile memory element, the means for controlling responsive to one of a boot master and at least one non-boot processing resource;
- means for segregating a portion of a solid-state non-volatile memory element, the portion including code and data for use by the at least one non-boot processing resource;
- means for monitoring when the solid-state non-volatile memory element is in use;
- and
- means for monitoring an operational condition of the at least one non-boot processing resource;
- wherein the computing device conditionally executes logic with the at least one non-boot processing resource to expose the code and data dedicated for execution and use by the at least one non-boot processing resource or executes logic with the boot master to expose content other than the code and data for use by the at least one non-boot processing resource from the solid-state non-volatile memory element.
Dependencies are inferred from the claim text.