Memory device capable of quickly repairing fail cell

A memory device, comprising:

• a memory array;
• a control logic configured to store fail cell information, the fail cell information identifying failed cells in the memory array;
• the control logic configured to transfer only fail cell column address information in the fail cell information to the memory array, the fail cell column address information indicating column addresses of the identified failed cells;
• the control logic configured to determine whether to perform a recovery operation based on address information in an access request and the fail cell column address information stored in the memory array, and the access request being a request to access the memory array;
• and
• a recovery circuit configured to perform the recovery operation if the control logic determines to perform the recovery operation.

A method, comprising:

• storing fail cell information in memory, the fail cell information identifying failed cells in the first region;
• transferring a portion of the fail cell information to a first region of a memory array;
• determining whether to perform a recovery operation based on address information in an access request and the portion of the fail cell information stored in the first region, and the access request being a request to access a second region of the memory array;
• and
• performing a recovery operation if the determining determines to perform the recovery operation.

A method, comprising:

• storing fail cell information in a memory, the fail cell information identifying failed cells in a memory array;
• transferring only fail cell column address information in the fail cell information to the memory array, the fail cell column address information indicating column addresses of the identified failed cells;
• determining whether to perform a recovery operation based on address information in an access request and the fail cell column address information stored in the memory array, the access request being a request to access the memory array;
• and
• performing the recovery operation if the control logic determines to perform the recovery operation.