Integrated circuit and method of detecting a data integrity error

An integrated circuit comprising:

• a write bus operably coupled to a register for storing control data;
• a storage unit arranged to store reference signature data encoding a reference collective state of the register;
• first logic circuitry arranged to generate actual signature data encoding the actual collective state of the register;
• second logic circuitry operably coupled to the storage unit and arranged to receive the actual signature data and compare the actual signature data with the reference signature data stored by the storage unit;
• and
• an alert inhibitor;
• wherein
• the second logic circuitry comprises an alert output to provide thereat an alert signal in response to the comparison identifying a difference between the actual signature data and the reference signature data, thereby ensuring detection of a data integrity error in respect of the register;
• and
• the alert inhibitor comprises a control input, the alert inhibitor being responsive to the control input and arranged to inhibit selectively onward propagation of the alert signal from the alert output.