Selective Sampling of Data Stored in Nonvolatile Memory
AssigneeSanDisk Technologies LLC
InventorsGautham Kumar Reddy, Niles Yang, Alexandra Bauche
Life of this patent
Estimating the term…
Abstract
Data stored in a nonvolatile memory is selectively sampled based on write-erase cycle counts of blocks. Blocks with the lowest write-erase cycle counts are sampled to determine an error rate which is compared with a limit. If the error rate exceeds the limit then the sample is expanded to include blocks with the next lowest write-erase cycle counts.
Claims25
A method of identifying high error rate data in a block-erasable nonvolatile memory comprising:
- (a) maintaining individual write-erase cycle counts for a plurality of blocks of the nonvolatile memory;
- (b) selecting a first subset of the plurality of blocks for error rate sampling, the first subset consisting of blocks with the lowest write-erase cycle counts of the plurality of blocks;
- (c) sampling data stored in the first subset of the plurality of blocks to estimate a first error rate for the first subset of the plurality of blocks;
- (d) comparing the first error rate with a first limit;
- (e) in response to determining that the first error rate exceeds the first limit, expanding the first subset to include additional blocks with next lowest write-erase cycle counts of the plurality of blocks;
- and
- (f) repeating steps (c)-(e).
The method of claim I wherein the block erasable nonvolatile memory is monolithically formed in two or more physical levels of memory cells having an active area disposed above a silicon substrate.
A block erasable nonvolatile memory system comprising:
- a plurality of individually erasable blocks of memory cells;
- a write-erase cycle count circuit that maintains individual write-erase cycle counts for each of the plurality of individually erasable blocks;
- a data sampling circuit that samples stored data from selected blocks of the plurality of individually erasable blocks;
- an error rate estimation circuit that estimates an error rate from data sampled by the data sampling circuit;
- and
- a selecting circuit that selects the selected blocks for the sampling circuit to sample based on corresponding individual write-erase cycle counts maintained by the write-erase cycle count circuit, the selected blocks comprising a subset of the plurality of individually erasable blocks with the lowest individual write-erase cycle counts of the plurality of individually erasable blocks, with additional blocks added to the subset when the error rate estimation circuit indicates that the error rate is greater than a limit.
A method of identifying high error rate data in a block-erasable nonvolatile memory comprising:
- (a) maintaining individual write-erase cycle counts for a plurality of blocks of the nonvolatile memory;
- (b) selecting a first subset of the plurality of blocks for error rate sampling, the first subset consisting of blocks with the lowest write-erase cycle counts of the plurality of blocks;
- (c) sampling data stored in the first subset of the plurality of blocks by reading at least one word line from each block of the first subset of the plurality of blocks to estimate a first error rate for the first subset of the plurality of blocks;
- (d) comparing the first error rate with a first limit;
- (e) in response to determining that the first error rate exceeds the first limit, expanding the first subset to include additional blocks with next lowest write-erase cycle counts of the plurality of blocks;
- (f) repeating steps (c)-(e) at write erase cycle count intervals;
- (g) selecting a second subset of the plurality of blocks for error rate sampling, the second subset consisting of blocks with the highest write-erase cycle counts of the plurality of blocks;
- (h) sampling data stored in the second subset of the plurality of blocks by reading at least one word line in each block of the second subset of the plurality of blocks to estimate a second error rate for the second subset of the plurality of blocks;
- (i) comparing the second error rate with a second limit;
- (j) in response to determining that the second error rate exceeds the second limit, expanding the second subset to include additional blocks with the next highest write-erase cycle counts of the plurality of blocks;
- (k) repeating steps (h)-(j) at write erase cycle count intervals;
- and
- (l) sorting blocks of the first plurality of blocks and the second plurality of blocks in order of individual error rates and subsequently performing data recovery operations on the blocks of the first plurality of blocks and the second plurality of blocks in the order of individual error rates.
Dependencies are inferred from the claim text.