Information processing system and information processing method

The information processing system according to 7, wherein

• the hardware processing means includes a plurality of FPGA devices,
• the hardware processing means are disposed to corresponding to the FPGA devices, respectively,
• the boundary apexes serving as boundaries between the hardware communities and the software communities are defined as first boundary apexes,
• an apex serving as a boundary between the adjacent FPGA devices is defined as a second boundary apex,
• in each of the FPGA devices and the software processing, processing for apexes including the first boundary apex is performed, and
• in each of the FPGA devices, processing for apexes including the second boundary apex is performed.

An information processing system comprising:

• a CPU, a memory device, a software computation means, an FPGA device, and a communication means,
• wherein the memory device have data to be processed, information pertaining to processing contents, and information pertaining to resources,
• wherein the information processing system includes
• a community selecting function of assigning, in the data to be processed, data in regions having heavy loads and reducible communication volumes to a hardware community and assigning data in the other regions to a software community, and
• a function of distributing the data to be processed such that the assigned data of the hardware community is processed by the FPGA device and the assigned data of the software community is processed by the software computation means.

A data processing method in an information processing system using an FPGA, wherein

• the information processing system includes a CPU, a memory device, a software computation means, an FPGA device, and a communication means,
• the memory device has data to be processed, information pertaining to processing contents, and information pertaining to resources,
• the data processing method comprising steps of:
• in the data to be processed, assigning data in regions having heavy loads and reducible communication volumes to a hardware community, and assigning data in the other regions to a software community, and
• distributing the data to be processed such that the assigned data of the hardware community is processed by the FPGA device and the assigned data of the software community is processed by the software computation means.