Methods And Apparatuses For Controlling Thread Contention
AssigneeIntel Corporation
InventorsAndrew Herdrich, Ramesh Illikkal, Donald Newell, Ravishankar Iyer, Vineet Chadha
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Abstract
An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
Claims20
A processor comprising:
- a plurality of cores;
- and
- a controller coupled to the plurality of cores including circuitry adapted to reduce an operating point of a first core of the plurality of cores based on a comparison of a performance metric of a second core of the plurality of cores to a set point, wherein the controller includes circuitry adapted to reduce a throttle state of the first core until a lowest throttle state is reached, and to thereafter reduce a performance state of the first core, wherein the controller comprises a proportional-integral-derivative (PID) controller.
A non-transitory machine-readable medium having stored thereon instructions, which when executed cause at least one machine to perform a method comprising:
- determining a control mode for a processor;
- adjusting an operating point of a first processor core of a plurality of processor cores of the processor based on comparison of a first number associated with cycles per instruction (CPI) of a second processor core of the plurality of processor cores to at least one of a first threshold and a second threshold, in a first control mode;
- and
- adjusting the operating point of the first processor core if a second number based on a system power value is higher than a third threshold, in a second control mode.
A system comprising:
- a processor including a plurality of cores, a shared cache memory, and a controller coupled to the plurality of cores having circuitry adapted to update an operating point of a first core of the plurality of cores based on a comparison of a performance metric of a second core of the plurality of cores to a set point, and based at least in part on a current operating point of the first core regulate clock throttling of the first core to prevent the set point from being exceeded in a first control mode or regulate power of the plurality of cores to prevent a system power constraint from being exceeded in a second control mode;
- and
- a communication device coupled to the processor.
Dependencies are inferred from the claim text.