Predicting literal load values using a literal load prediction table, and related circuits, methods, and computer-readable media

An instruction processing circuit comprising:

• a means for detecting, in an instruction stream, a first occurrence of a literal load instruction;
• a means for determining whether an address of the literal load instruction is present in an entry of a literal load prediction table;
• a means for, responsive to determining that the address of the literal load instruction is present in the entry, providing a predicted literal load value stored in the entry for execution of at least one dependent instruction on the literal load instruction;
• a means for, further responsive to determining that the address of the literal load instruction is present in the entry, determining, upon execution of the literal load instruction, whether the predicted literal load value matches an actual literal load value loaded by the literal load instruction;
• a means for, responsive to determining that the predicted literal load value does not match the actual literal load value, initiating a misprediction recovery;
• and
• a means for, further responsive to determining that the predicted literal load value does not match the actual literal load value, re-executing the at least one dependent instruction using the actual literal load value.

A method for predicting values of literal loads, comprising:

• detecting, in an instruction stream, a first occurrence of a literal load instruction;
• determining whether an address of the literal load instruction is present in an entry of a literal load prediction table;
• and
• responsive to determining that the address of the literal load instruction is present in the entry:
• providing a predicted literal load value stored in the entry for execution of at least one dependent instruction on the literal load instruction;
• determining, upon execution of the literal load instruction, whether the predicted literal load value matches an actual literal load value loaded by the literal load instruction;
• and
• responsive to determining that the predicted literal load value does not match the actual literal load value:
• initiating a misprediction recovery;
• and
• re-executing the at least one dependent instruction using the actual literal load value.

A non-transitory computer-readable medium having stored thereon computer-executable instructions to cause a processor to:

• detect, in an instruction stream, a first occurrence of a literal load instruction;
• determine whether an address of the literal load instruction is present in an entry of a literal load prediction table;
• and
• responsive to determining that the address of the literal load instruction is present in the entry:
• provide a predicted literal load value stored in the entry for execution of at least one dependent instruction on the literal load instruction;
• determine, upon execution of the literal load instruction, whether the predicted literal load value matches an actual literal load value loaded by the literal load instruction;
• and
• responsive to determining that the predicted literal load value does not match the actual literal load value:
• initiate a misprediction recovery;
• and
• re-execute the at least one dependent instruction using the actual literal load value.