Double rounded combined floating-point multiply and add

An apparatus comprising:

• a floating-point (FP) multiplier circuit to multiply a first operand multiplicand mantissa by a second operand multiplier mantissa to generate a product;
• a FP alignment circuit to align a third operand mantissa according to the product of the FP multiplier circuit;
• an overflow detection circuit to detect an overflow condition in the product of the FP multiplier circuit;
• a first FP adder circuit to add together the aligned third operand mantissa and the product of the FP multiplier circuit using a first rounding input to generate a first sum or difference based on an assumption that the overflow condition in the product of the FP multiplier circuit was not detected;
• a second FP adder circuit to add together the aligned third operand mantissa and the product of the FP multiplier circuit using a second rounding input to generate a second sum or difference based on an assumption that the overflow condition in the product of the FP multiplier circuit was detected;
• and
• a multiplexer circuit to select between the second sum or difference and the first sum or difference based on the overflow detection circuit detecting, or not detecting the overflow condition, respectively, in the product of the FP multiplier circuit.

A processor comprising:

• one or more vector registers each comprising a plurality of data fields to store values of vector elements;
• a decode stage to decode a single instruction multiple data (SIMD) double-rounded combined floating-point (FP) multiply-add or multiply-subtract instruction specifying:
• a destination operand of the one or more vector registers, a first operand multiplicand of the one or more vector registers, a size of the vector elements, a second operand multiplier of the one or more vector registers, and a third operand of the one or more vector registers;
• a SIMD FP multiply-adder comprising:
• a floating-point (FP) multiplier stage to multiply a plurality of mantissas of the first operand multiplicand with a plurality of respective mantissas of the second operand multiplier to generate a plurality of respective products;
• a FP alignment stage to align a plurality of respective mantissas of the third operand according to the respective products of the FP multiplier stage;
• an overflow detection stage to detect overflow conditions in the respective products of the FP multiplier stage;
• a first FP adder stage to add together the plurality of respective aligned mantissas of the third operand and the respective products of the FP multiplier stage using a first set of rounding inputs to generate a first plurality of respective sums or differences based on an assumption that overflow conditions in the respective products of the FP multiplier circuit were not detected;
• a second FP adder stage to add together the plurality of respective aligned mantissas of the third operand and the respective products of the FP multiplier stage using a second set of rounding inputs to generate a second plurality of respective sums or differences based on an assumption that overflow conditions in the respective products of the FP multiplier circuit were detected;
• and
• a multiplexer stage to select between the second sums or differences and the first sums or differences, of the respective pluralities, based on the overflow detection stage detecting, or not detecting respective overflow conditions in the respective products of the FP multiplier stage.