Interface to expose interrupt times to hardware
AssigneeAdvanced Micro Devices, Inc.
InventorsIndrani Paul, Manish Arora
Life of this patent
Estimating the term…
Abstract
A power management controller is used to control power management states of a processing device. A register stores a timer tick value accessible to the power management controller. The timer tick value indicates when an interrupt is to occur in the processing device. The power management controller may use the exposed timer tick value to decide whether to transition between power management states such as an active state, an idle state, and a power-gated state. The timer tick value stored in the register may be modified by an operating system, an application, or software implemented on the processing device.
Claims20
A method comprising:
- storing a timer tick value in a register accessible to a power management controller in a processing device, wherein the timer tick value indicates when an interrupt is to occur in the processing device.
An apparatus comprising:
- a power management controller to control power management states of a processing device;
- and
- a register to store a timer tick value accessible to the power management controller, wherein the timer tick value indicates when an interrupt is to occur in the processing device.
A non-transitory computer readable medium embodying a set of executable instructions, the set of executable instructions to manipulate at least one processor to:
- store a timer tick value in a register accessible to a power management controller in a processing device, wherein the timer tick value indicates when an interrupt is to occur in the processing device.
Dependencies are inferred from the claim text.