Frequency configuration of asynchronous timing domains under power constraints
AssigneeAdvanced Micro Devices, Inc.
InventorRamkumar Jayaseelan
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Abstract
A processing device includes one or more queues to convey data between a producing processor unit in a first timing domain and a consuming processor unit in a second timing domain that is asynchronous with the first timing domain. A system management unit configures a first operating frequency of the producing processor unit and a second operating frequency of the consuming processor unit based on a power constraint for the processing device and a target size of the one or more queues.
Claims20
A method comprising:
- configuring a first operating frequency of a producing processor unit in a first timing domain of a processing device and a second operating frequency of a consuming processor unit in a second timing domain of the processing device that is asynchronous with the first timing domain based on a power constraint for the processing device and a target size of a queue that conveys data between the producing processor unit and the consuming processor unit.
An apparatus comprising:
- at least one queue to convey data between a producing processor unit in a first timing domain of a processing device and a consuming processor unit in a second timing domain of the processing device that is asynchronous with the first timing domain;
- and
- a system management unit to configure a first operating frequency of the producing processor unit and a second operating frequency of the consuming processor unit based on a power constraint for the processing device and a target size of the at least one queue.
A non-transitory computer readable medium embodying a set of executable instructions, the set of executable instructions to manipulate at least one processor to:
- configure a first operating frequency of a producing processor unit in a first timing domain of a processing device and a second operating frequency of a consuming processor unit in a second timing domain of the processing device that is asynchronous with the first timing domain based on a power constraint for the processing device and a target size of a queue that conveys data between the producing processor unit and the consuming processor unit.
Dependencies are inferred from the claim text.