Power and performance management of asynchronous timing domains in a processing device
AssigneeAdvanced Micro Devices, Inc.
InventorsWayne P. Burleson, Manish Arora, Indrani Paul, Yasuko Eckert
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Abstract
A processing device includes a producing processor unit in a first timing domain and a consuming processor unit in a second timing domain that is asynchronous with the first timing domain. A queue is used to convey data between the producing processor unit and the consuming processor unit. A system management unit is to modify one or both of an operating frequency or an operating voltage of one or both of the producing processor unit or the consuming processor unit based on a rate of change of a fullness of the queue.
Claims20
A method comprising:
- modifying at least one of an operating frequency and an operating voltage of at least one of a producing processor unit in a first timing domain and a consuming processor unit in a second timing domain that is asynchronous with the first timing domain based on a rate of change of a fullness of a queue that conveys data between the producing processor unit and the consuming processor unit.
An apparatus comprising:
- at least one queue to convey data between a producing processor unit in a first timing domain and a consuming processor unit in a second timing domain that is asynchronous with the first timing domain;
- and
- a system management unit to modify at least one of an operating frequency and an operating voltage of at least one of the producing processor unit and the consuming processor unit based on a rate of change of a fullness of the at least one queue.
A non-transitory computer readable medium embodying a set of executable instructions, the set of executable instructions to manipulate at least one processor to:
- modify at least one of an operating frequency and an operating voltage of at least one of a producing processor unit in a first timing domain and a consuming processor unit in a second timing domain that is asynchronous with the first timing domain based on a rate of change of a fullness of a queue that conveys data between the producing processor unit and the consuming processor unit.
Dependencies are inferred from the claim text.