Clock gating circuits and circuit arrangements including clock gating circuits
OwnerJiann-Tyng Tzeng, Meng-Hung Shen +2inventors
InventorsJiann-Tyng Tzeng, Meng-Hung Shen, Yi-Feng Chen, Charles Chew-Yuen Young
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Abstract
Clock gating circuits may include: a first inverter; a first switch having a first terminal and a second terminal, the first terminal of the first switch coupled to an output of the first inverter; a feedback circuit having an input-output terminal, the input-output terminal of the feedback circuit coupled to the second terminal of the first switch; and a first logic gate having a first input terminal and a second input terminal, the first input terminal coupled to the input-output terminal of the feedback circuit, the second input terminal electrically connected to receive a master clock signal.
Claims20
A clock gating circuit comprising:
- a first inverter;
- a first switch having a first terminal and a second terminal, the first terminal of the first switch coupled to an output of the first inverter;
- a feedback circuit having an input-output terminal, the input-output terminal of the feedback circuit coupled to the second terminal of the first switch;
- and
- a first logic gate having a first input terminal and a second input terminal, the first input terminal coupled to the input-output terminal of the feedback circuit, the second input terminal electrically connected to receive a master clock signal.
A clock gating circuit, comprising:
- a first inverter;
- a first transmission gate having a first terminal and a second terminal, the first terminal of the first transmission gate coupled to an output of the first inverter;
- a second inverter, an input of the second inverter coupled to the second terminal of the first transmission gate;
- a third inverter, an input of the third inverter coupled to an output of the second inverter;
- a second transmission gate having a first terminal and a second terminal, the first terminal of the second transmission gate coupled to an output of the third inverter, the second terminal of the second transmission gate coupled to the input of the second inverter;
- and
- a first logic gate having a first input terminal and a second input terminal, the first input terminal of the first logic gate coupled to the second terminal of the second transmission gate, the second input terminal of the first logic gate electrically connected to receive a master clock signal.
A circuit arrangement comprising:
- a clock gating circuit comprising:
- a NOR gate;
- a first inverter, wherein an output terminal of the NOR gate is coupled to an input of the first inverter;
- a first switch having a first terminal and a second terminal, the first terminal of the first switch coupled to an output of the first inverter;
- a second inverter, an input of the second inverter coupled to the second terminal of the first switch;
- a third inverter, an input of the third inverter coupled to an output of the second inverter;
- a second switch having a first terminal and a second terminal, the first terminal of the second switch coupled to an output of the third inverter, the second terminal of the second switch coupled to the input of the second inverter;
- a NAND gate having a first input terminal and a second input terminal, the first input terminal of the NAND gate coupled to the second terminal of the second switch, the second input terminal of the NAND gate electrically connected to receive a master clock signal;
- and
- a fourth inverter, an input of the fourth inverter coupled to an output of the NAND gate;
- and
- at least one flip flop coupled to an output of the fourth inverter of the clock gating circuit.
Dependencies are inferred from the claim text.