Programmable logic controller having low latency

A method for operating a programmable logic control apparatus, comprising:

• receiving a current input data record having state data from a peripheral area from a communication bus each time a bus cycle time elapses
• cyclically executing a first program instance of a control program and at least one further instance of the control program, the program instances each copying a current input data record and computing an output data record having control data computed from the copied input data record during a respective program cycle,
• transferring the output data record to the communication bus for transmission to the peripheral area at the end of the program cycle of the respective program instance, the program cycle time being longer than the bus cycle time, so that, between the beginning and end of the program cycle, the first program instance receives at least one further current input data record from the communication bus, said further current input data record being ignored by the first program instance because the first program instance program cycle has not yet terminated,
• providing a timing shift of less than one program cycle time for the execution of the at least one further program instance with respect to the first program instance, and
• receiving an input data record for processing by one of the program instances, different input data records received from the communication bus being processed by the first program instance and by the at least one further program instance, respectively, the data record being processed by the at least one other program instance being received between the beginning and end of the program cycle of the first program instance.

A control apparatus for a process and/or production installation, having a bus port for interchanging input and output data records with a peripheral area of the installation via a communication bus and having a processor system for executing program instances of a control program, the control apparatus being constructed to:

• receive a current input data record having state data from a peripheral area from a communication bus each time a bus cycle time elapses
• cyclically execute a first program instance of a control program and at least one further instance of the control program, the program instances copying the current input data record and computing an output data record having control data computed from the copied input data record during the respective program cycle,
• transfer the output data record to the communication bus for transmission to the peripheral area at the end of the cycle, the program cycle time being longer than the bus cycle time, so that, between the beginning and end of the program cycle, the first program instance receiving at least one further current input data record from the communication bus, said further current input data record being ignored by the first program instance because the first program instance program cycle has not yet terminated,
• provide a timing shift of less than one program cycle time for the execution of the at least one further program instance with respect to the first program instance, and
• receive an input data record for processing by one of the program instances, different input data records being received from the communication bus being processed by the first program instance and by the at least one further program instance, respectively, the data record being processed by the at least one other program instance being received between the beginning and end of the program cycle of the first program instance.