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US 2016/0072605 A1Published application
Time-Division Multiplexing Data Aggregation Over High Speed Serializer/Deserializer Lane
AssigneeArtesyn Embedded Computing, Inc.
InventorsStephan KRUECKER, Armin JACHT, Reinhold HOFER
Life of this patent
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Abstract
A digital signal interface includes a multiplexer coupled to receive a plurality of data signals from at least one of a microprocessor, a microcontroller, or a field-programmable gate array (FPGA), the multiplexer multiplexing the plurality of data signals. The interface further includes a serializer/deserializer (SerDes) transceiver coupled to receive the multiplexed data signals, the SerDes transceiver serializing the multiplexed data signals and transmitting the serialized data signals.
Claims18
A digital signal interface, comprising:
- a multiplexer coupled to receive a plurality of data signals from at least one of a microprocessor, a microcontroller, or a field-programmable gate array (FPGA), the multiplexer multiplexing the plurality of data signals;
- a serializer/deserializer (SerDes) transceiver coupled to receive the multiplexed data signals, the SerDes transceiver serializing the multiplexed data signals and transmitting the serialized data signals.
A digital signal interface, comprising:
- a multiplexer coupled to receive a plurality of data signals from at least one of a microprocessor, a microcontroller, or a field-programmable gate array (FPGA), the multiplexer multiplexing the plurality of data;
- a serializer/deserializer (SerDes) transceiver coupled to receive the multiplexed data signals, the SerDes transceiver serializing the multiplexed data signals and transmitting the serialized data signals,
- wherein the microprocessor, the microcontroller, or the FPGA supports a time-division multiplexing (TDM) bus protocol.
Dependencies are inferred from the claim text.