Selectable phase or cycle jitter detector
AssigneeApple Inc.
InventorsGreg M. Hess, James E. Burnette, II
Life of this patent
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Abstract
Embodiments of a jitter detection circuit are disclosed that may allow for detecting both cycle and phase jitter in a clock distribution network. The jitter detection circuit may include a phase selector, a data generator, a delay chain, a logic circuit, and clocked storage elements. The phase selector may be operable to select a clock phase to be used for the launch clock, and the data generator may be operable to generate a data signal responsive to the launch clock. The delay chain may generate a plurality of outputs dependent upon the data signal, and the clocked storage elements may be operable to capture the plurality of outputs from the delay chain, which may be compared to expected data by the logic circuit.
Claims19
An apparatus, comprising:
- a clock generation circuit configured to generate a clock signal;
- and
- one or more jitter detection circuits configured to:
- generate a launch clock dependent on the clock signal and a launch phase selection signal;
- generate a data signal dependent upon the launch clock;
- generate a capture clock dependent on the clock signal;
- generate a plurality of delayed signals dependent upon the data signal;
- capture a respective one of the plurality of delayed signals responsive to the capture clock to generate a plurality of captured signals;
- and
- identify one or more delayed signals of the plurality of delayed signals that were incorrectly captured dependent upon the plurality of captured signals.
A method for operating a plurality of jitter detection circuits, the method comprising:
- generating a plurality of launch clocks dependent upon a clock signal, a plurality of first launch phase signals, and a plurality of second launch phase signals;
- generating a plurality of data signals dependent upon a respective launch clock of the plurality of launch clocks;
- generating a plurality of capture clocks dependent upon the clock signal;
- generating a plurality of sets of delayed data signals, wherein each delayed data signal of a given set of the plurality of sets delayed data signals is dependent upon a respective one of the plurality of data signals;
- capturing each delayed data signal of a given set of the plurality of sets of delayed data signals dependent upon a given one of the plurality of capture clocks to generate a corresponding set of captured data signals;
- and
- identifying one or more delayed data signals of the given set of the plurality of sets delayed data signals that were incorrectly captured dependent upon the corresponding set of captured data signals.
A system, comprising:
- a processor coupled to receive a clock input;
- one or more memories, wherein each memory of the one or more memories is coupled to receive the clock input;
- and
- one or more jitter detection circuits, comprising:
- a launch clock generation circuit configured to generate a launch clock dependent on the clock input and a launch phase selection signal;
- a data generation circuit configured to generate a data signal dependent upon the launch clock;
- a capture clock generation circuit configured to generate a capture clock dependent on the clock input;
- a delay chain configured to receive the data signal and generate a plurality of delayed signals;
- a plurality of clocked storage devices each of which is configured to capture a respective one of the plurality of delayed signals responsive to the capture clock;
- and
- a logic circuit coupled to receive outputs of the plurality of clocked storage devices and configured to identify a clocked storage device of the plurality of clocked storage devices that captures the respective delayed signal in error, wherein the clock storage device captures the least delayed signal of the plurality of delayed clocks that are captured in error.
Dependencies are inferred from the claim text.