US 2016/0055270 A1Published application

Logic circuit and system and computer program product for logic synthesis

AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University

InventorsChi-Chuan CHUANG, Yi-Hsiang LAI, Jie-Hong CHIANG

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Abstract

A logic circuit includes first and second input, an output, an input acknowledgement node, an output acknowledgement node, a logic evaluation block, a pre-charging circuit, and a completion detection circuit. The logic evaluation block performs a logic evaluation of first and second input signals at the first and second inputs, and to output an output signal corresponding to the logic evaluation. The pre-charging circuit pre-charges the logic evaluation block in response to the first input signal and an acknowledgement signal at the input acknowledgement node. The completion detection circuit generates an acknowledgement signal at the output acknowledgement node in response to the second input signal and the output signal.

Claims20

Dependent claims

A logic circuit, comprising:

at least one first input;
at least one second input;
an output;
an input acknowledgement node configured to be coupled to a next logic stage;
an output acknowledgement node configured to be coupled to a previous logic stage;
a logic evaluation block coupled to the at least one first input, the at least one second input, and the output,
the logic evaluation block configured to perform a logic evaluation of first and second input signals at the corresponding at least one first input and at least one second input, and to output an output signal corresponding to a result of the logic evaluation;
a pre-charging circuit coupled to the at least one first input, the input acknowledgement node, and the logic evaluation block,
the pre-charging circuit configured to pre-charge the logic evaluation block in response to the first input signal and a next stage acknowledgement signal at the input acknowledgement node;
and
a completion detection circuit coupled to the at least one second input, the output, and the output acknowledgement node,
the completion detection circuit configured to generate a previous stage acknowledgement signal at the output acknowledgement node in response to the second input signal and the output signal.

9 more elements

A computer program product, comprising a non-transitory, computer-readable medium containing instructions therein which, when executed by at least one processor, cause the at least one processor to perform:

a performance analysis of a network of interconnected nodes, the nodes configured to perform corresponding logic functions, wherein the performance analysis comprises, for each of the nodes in a pipeline in the network:
calculating an evaluation finish time of said node based on the evaluation finish time of a fanin node of said node, and an evaluation time parameter of the module at said node,
calculating a pre-charging finish time of said node based on the evaluation finish time of a fanout node of said node, an acknowledge output time parameter of the module at the fanout node, the evaluation finish time of the fanin node of said node, an acknowledge output time parameter of said node, the evaluation finish time of said node, and a pre-charging time parameter of the module at said node, and
calculating a cycle time of said node based on the pre-charging finish time and the acknowledge output time parameter of the fanout node, and the evaluation finish time of the fanin node.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 14/464,366Filed 20 Aug 2014
Published: 25 Feb 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/33
Circuit design at the digital level: design verification, e.g. functional simulation or model checking
G06F 30/3312
Using simulation: timing analysis
G06F 30/3323
Design verification, e.g. functional simulation or model checking: using formal methods, e.g. equivalence checking or property checking