Digital filter
AssigneeIntel Deutschland GmbH
InventorAndreas Menkhoff
Life of this patent
Estimating the term…
Abstract
Methods and apparatuses in which a first stage of a digital filter receives input data to be filtered, the first stage of a digital filter operating at a first clock; a second stage of the digital filter outputs filtered output data, the second stage of the digital filter operating on a second clock, wherein a ratio of a frequency of the first clock and a frequency of the second clock is a fractional number, and a frequency of the second clock is higher than a frequency of the first clock; the first stage receives an indication of a ratio of the first clock and the second clock; and the first stage receives an indication of a time offset between (1) a clock pulse of the second clock, which occurs between a first clock pulse and a second clock pulse of the first clock, and (2) the first clock pulse of the first clock.
Claims21
1-25. (canceled)
An apparatus, comprising:
- a first stage to receive an input, the first stage including:
- a register, at most two multipliers, at least two adders, coupled together to provide first and second inputs in response to the received input;
- a first sampler to receive the first input and to sample it to provide a first sampled input;
- a second sampler to receive the second input and to sample it to provide a second sampled input;
- a second stage including an adder and a register which are to receive the first and second sampled inputs, respectively, and to generate an output.
A method comprising:
- receiving an input by a first stage, wherein the first stage includes:
- a register, at most two multipliers, at least two adders, coupled together to provide first and second inputs in response to the received input;
- sampling the first input to provide a first sampled input;
- sampling the second input to provide a second sampled input;
- receiving by a second stage the first and second sampled inputs and to generate an output.
An apparatus comprising:
- a first stage to receive an input, the first stage including at most two multipliers, the first stage is to provide first and second inputs in response to the received input;
- and
- a second stage including an adder and a register which are to receive sampled versions of the first and second inputs, respectively, and to generate an output.
Dependencies are inferred from the claim text.