Semiconductor integrated circuit device

A semiconductor integrated circuit device provided with a plurality of lead layers over a semiconductor substrate, comprising:

• a plurality of first memory cells arranged along a first direction;
• a plurality of second memory cells arranged along the first direction;
• a first bit line and a second bit line, each commonly connected to the plurality of first memory cells;
• a third bit line and a fourth bit line, each commonly connected to the plurality of second memory cells;
• a plurality of word lines extending in a second direction, each of the plurality of word lines being connected to one of the plurality of first memory cells and one of the plurality of second memory cells, respectively;
• first, second and third P-well regions provided on a main surface of the semiconductor substrate;
• a first N-well region provided on the main surface of the semiconductor substrate and arranged between the first and second P-well regions;
• a second N-well region provided on the main surface of the semiconductor substrate and arranged between the second and third P-well regions;
• a first voltage supply lead comprised of a first lead layer of the plurality of the lead layers;
• a first supply path physically contacting a first portion of the first voltage supply lead opposite to the semiconductor substrate and configured to supply a first voltage to the first P-well region from the first voltage supply lead;
• a second supply path physically contacting a second portion of the first voltage supply lead, which is different from the first portion, opposite to the semiconductor substrate and configured to supply the first voltage to the second P-well region from the first voltage supply lead;
• a third supply path connecting to a third portion of the first voltage supply lead, which is different from the first and the second portions, opposite to the semiconductor substrate and configured to supply the first voltage to the third P-well region from the first voltage supply lead;
• a second voltage supply lead comprised of the first lead layer of the plurality of the lead layers;
• wherein the first, the second and the third portions are provided to be aligned linearly along the second direction in plan view,
• wherein the plurality of word lines are formed with the first lead layer,
• wherein each of the plurality of first memory cells includes:
• first and second P-channel transistors provided on the first N-well region,
• first and second N-channel transistors provided on the first P-well region, and
• third and fourth N-channel transistors provided on the second P-well;
• wherein the first N-channel transistor and the first P-channel transistor configure a first inverter, the third N-channel transistor and the second P-channel transistor configure a second inverter with an input of the first inverter coupled to an output of the second inverter and with an output of the first inverter coupled to an input of the second inverter,
• the second N-channel transistor electrically connects the first bit line with the output of the first inverter, and
• the fourth N-channel transistor electrically connects the second bit line with the output of the second inverter with a gate of the fourth N-channel transistor coupled to a gate of the second N-channel transistor, and
• wherein each of the plurality of second memory cells includes:
• third and fourth P-channel transistors provided on the second N-well region,
• fifth and sixth N-channel transistors provided on the second P-well region, and
• seventh and eighth N-channel transistors provided on the third P-well;
• wherein the fifth N-channel transistor and the third P-channel transistor configure a third inverter, the seventh N-channel transistor and the fourth P-channel transistor configure a fourth inverter with an input of the third inverter coupled to an output of the fourth inverter and with an output of the third inverter coupled to an input of the fourth inverter, and
• wherein the sixth N-channel transistor electrically connects the third bit line with the output of the third inverter, and the eighth N-channel transistor electrically connects the fourth bit line with the output of the fourth inverter with a gate of the eighth N-channel transistor couple to a gate of the sixth transistor.