Method And System For A Low Input Voltage Low Impedance Termination Stage For Current Inputs

A semiconductor device, the device comprising:

• an output stage for an electrical circuit, the output stage comprising input cascode transistors and stacked output transistors, wherein a source-follower feedback path for the input cascode transistors comprises a feedback transistor with its gate terminal coupled to a drain terminal of a first of the input cascode transistors, a drain of the feedback transistor coupled to a supply voltage, and a source terminal of the feedback transistor coupled to a current source.

The semiconductor device according to claim 1, wherein a current source is coupled to the drain of the first of the input cascode transistors.

The semiconductor device according to claim 1, wherein the supply voltage is coupled to the stacked output transistors via a load resistor.

The semiconductor device according to claim 1, wherein the input cascode transistors, the feedback transistor, and the stacked output transistors comprise complementary metal-oxide semiconductor (CMOS) transistors.

The semiconductor device according to claim 1, wherein a current through the input cascode transistors is controlled by a bias voltage applied to a gate terminal of the first of the input cascode transistors.

The semiconductor device according to claim 1, wherein the electrical circuit comprises a power amplifier.

The semiconductor device according to claim 6, wherein the power amplifier comprises a differential gain stage coupled to a source terminal of the first of the cascode transistors and a drain of a second of the cascode transistors.

The semiconductor device according to claim 1, wherein the electrical circuit comprises a digital-to-analog converter (DAC).

The semiconductor device according to claim 8, wherein the DAC comprises a plurality of unit cells, each cell coupled to a source terminal of the first of the cascode transistors and a drain of a second of the cascode transistors.

The semiconductor device according to claim 9, wherein each of the plurality of unit cells are also coupled to cascode transistors in a second output stage nominally identical to the output stage.

The semiconductor device according to claim 1, wherein a feedback circuit comprising a resistor and capacitor in series is coupled from the pair of input cascode transistors to a load resistance that is coupled to the stacked output transistors.

The method according to claim 12, wherein a current source is coupled to the drain of the first of the input cascode transistors.

The method according to claim 12, wherein the supply voltage is coupled to the stacked output transistors via a load resistor.

The method according to claim 12, wherein the input cascode transistors, the feedback transistor, and the stacked output transistors comprise complementary metal-oxide semiconductor (CMOS) transistors.

The method according to claim 12, comprising controlling a current through the input cascode transistors with a bias voltage applied to a gate terminal of the first of the input cascode transistors.

The method according to claim 12, wherein the electrical circuit comprises a power amplifier.

The method according to claim 17, wherein the power amplifier comprises a differential gain stage coupled to a source terminal of the first of the cascode transistors and a drain of a second of the cascode transistors.

The method according to claim 12, wherein the electrical circuit comprises a digital-to-analog converter (DAC).

The method according to claim 19, wherein the DAC comprises a plurality of unit cells, each cell coupled to a source terminal of the first of the cascode transistors and a drain of a second of the cascode transistors and wherein each of the plurality of unit cells are also coupled to cascode transistors in a second output stage nominally identical to the output stage.

The method according to claim 12, wherein a feedback circuit comprising a resistor and capacitor in series is coupled from the input cascode transistors to a load resistance that is coupled to the stacked output transistors.