Digital filter with a pipeline structure, and a corresponding device
AssigneeSTMicroelectronics S.r.l.
InventorFrancesco Pirozzi
Life of this patent
Estimating the term…
Abstract
A digital filter with a pipeline structure includes processing structures timed by respective clock signals. Each processing structure in turn is formed by a number of processing modules for processing input samples. A phase generator aligns the processing modules with the input samples so that each input sample is processed by a respective one of the processing modules. An up-sampling buffer and a down-sampling buffer are used when the processing structures operate at different clock frequencies (thus implementing different clock domains) so as to convert signal samples between the clock domains for processing in the processing structures.
Claims15
A digital filter, comprising:
- a pipeline structure including a plurality of processing structures each timed by a respective clock signal, wherein each processing structure includes plural processing modules for processing input samples,
- a phase generator configured to align said processing modules to said input samples so that each said input sample is processed by a respective one of the processing modules in said processing structures,
- up-sampling and down-sampling buffers configured to be activated when said processing structures operate at different clock frequencies,
- a first clock domain, and
- a second clock domain,
- said up-sampling and down-sampling buffers configured to convert signal samples between said first clock domain and said second clock domain.
A filter, comprising:
- a first processing structure operating in accordance with a first clock and including a plurality of first processing modules arranged in a first rotating processing scheme timed by said first clock;
- a second processing structure operating in accordance with a second clock, wherein the second clock has a lower frequency than the first clock, and including a plurality of second processing modules arranged in a second rotating processing scheme timed by said second clock;
- a down-sampling buffer configured to receive first input data at the first clock and output first output data at the second clock for processing through the second processing structure;
- and
- an up-sampling buffer configured to receive second input data output from the second processing structure at the second clock and output second output data at the first clock.
Dependencies are inferred from the claim text.