Data Bus Efficiency Via Cache Line Usurpation
AssigneeEmulex Corporation
InventorsSteven Gerard LeMire, Vuong Cao Nguyen
Life of this patent
Estimating the term…
Abstract
Embodiments of the current invention permit a user to allocate cache memory to main memory more efficiently. The processor or a user allocates the cache memory and associates the cache memory to the main memory location, but suppresses or bypassing reading the main memory data into the cache memory. Some embodiments of the present invention permit the user to specify how many cache lines are allocated at a given time. Further, embodiments of the present invention may initialize the cache memory to a specified pattern. The cache memory may be zeroed or set to some desired pattern, such as all ones. Alternatively, a user may determine the initialization pattern through the processor.
Claims22
1-14. (canceled)
A system comprising:
- a cache;
- a storage device;
- and
- a memory controller coupled to the cache and operable determine whether a piece of data is required for a system operation,
- if the piece of data is not required for the system operation, the memory controller being operable to write the piece of data directly to the storage device while the cache is allocated, and
- if the piece of data is required for the system operation, the memory controller being operable to write the piece of data into the cache.
19-24. (canceled)
A method for cache allocation, the method comprising:
- determining whether a piece of data is required for a system operation,
- writing the piece of data directly to a storage device while a cache location is allocated, if the piece of data is not required for the system operation, and
- writing the piece of data into the cache location, if the piece of data is required for the system operation.
A network device with cache allocation, the network device comprising:
- a cache;
- a storage device;
- and
- a hardware processor operable to write a piece of data directly to a storage device while the cache is allocated, if the piece of data is not required for the system operation, the hardware processor being operable to write the piece of data into the cache, if the piece of data is required for the system operation.
Dependencies are inferred from the claim text.