System and Method for Error Recovery in an Asynchronous FIFO
AssigneeEmulex Corporation
InventorShiro Suzuki
Life of this patent
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Abstract
A system and method for error recovery in an asynchronous first-in, first-out device (FIFO) are described herein. The FIFO may comprise a FIFO memory that is controlled with a FIFO controller. In accordance with this disclosure, the FIFO memory may receive input data, temporarily store the input data, and transmit the temporarily stored input data as output data. The FIFO controller comprises a plurality of control registers. During operation, the FIFO controller may detect a bit error in a control register of the plurality of control registers and set a flag associated with the output data. The FIFO controller may subsequently correct the bit error without requiring a reset to a system environment comprising the FIFO.
Claims20
A system comprising:
- a first-in, first-out (FIFO) memory operable to receive input data;
- temporarily store the input data;
- and transmit the temporarily stored input data as output data;
- and
- a FIFO controller comprising a plurality of control registers, the FIFO controller being operable to detect a bit error in a control register of the plurality of control registers, set a flag associated with the output data and correct the bit error.
A method comprising:
- receiving input data;
- temporarily storing the input data in a first-in, first-out (FIFO) device;
- detecting a bit error in a control register associated with the FIFO device;
- setting a flag associated with the temporarily stored input data;
- and
- correcting the bit error in the control register.
Dependencies are inferred from the claim text.