Implementation for a high performance bcd divider
AssigneeOracle International Corporation
InventorsChristopher H. Olson, Jeffrey S. Brooks, Albert Danysh
Life of this patent
Estimating the term…
Abstract
Embodiments of an apparatus are disclosed for performing arithmetic operations on provided operands. The apparatus may include a fetch unit, and an arithmetic logic unit (ALU). The fetch unit may be configured to retrieve two operands responsive to receiving an instruction, wherein the operands include binary-coded decimal values. The ALU may be configured to scale a value of each of the operands, and then compress the scaled values of the operands. The compressed values of the operands may include fewer data bits than the corresponding scaled values. The ALU may be further configured to estimate a portion of a result of the operation dependent upon the compressed values of the operands.
Claims20
An apparatus, comprising:
- a fetch unit configured to retrieve a first operand and a second operand responsive to receiving an instruction, wherein a value of the first operand and a value of the second operand each include respective binary-coded decimal (BCD) values;
- an arithmetic logic unit (ALU) configured to:
- scale the value of the first operand and the value of the second operand to generate a first scaled value and a second scaled value, respectively;
- compress the first scaled value and the second scaled value to generate a first compressed value and a second compressed value, respectively;
- wherein a number of data bits included in the first compressed value is less than a number of data bits included in the first scaled value, and a number of data bits included in the second compressed value is less than a number of data bits included in the second sclaed value;
- and
- estimate a portion of a result of the operation dependent upon the first compressed value and the second compressed value.
A method, comprising:
- receiving a first operand, a second operand, and an operation, wherein a value of the first operand and a value of the second operand each include respective binary-coded decimal values;
- scaling the value of the first operand and the value of the second operand to generate a first scaled value and a second scaled value, respectively;
- compressing the first scaled value and the second scaled value to generate a first compressed value and a second compressed value, respectively;
- wherein a number of data bits included in the first compressed value is less than a number of data bits included in the first scaled value, and a number of data bits included in the second compressed value is less than a number of data bits included in the second scaled value;
- and
- estimating a portion of a result of the operation dependent upon the first compressed value and the second compressed value.
A system, comprising:
- a processor;
- a memory configured to store one or more program instructions;
- and
- an interface configured to couple the processor and the memory;
- wherein the processor is configured to:
- retrieve a first operand, a second operand, and an operation dependent upon at least one of the one or more program instructions;
- scale the value of the first operand and the value of the second operand to generate a first scaled value and a second scaled value, respectively;
- compress the first scaled value and the second scaled value to generate a first compressed value and a second compressed value, respectively;
- wherein a number of data bits included in the first compressed value is less than a number of data bits included in the first scaled value, and a number of data bits included in the second compressed value is less than a number of data bits included in the second scaled value;
- and
- estimate a portion of a result of the operation dependent upon the first compressed value and the second compressed value.
Dependencies are inferred from the claim text.