Soft Error Protection For Content Addressable Memory

A system comprising:

• a cache;
• a memory device;
• a content addressable memory (CAM) operable to store address entries;
• and
• a controller operable to compare received address with the stored address entries and to generate a miss signal if no stored address entry matches the received address, the controller being coupled to the CAM and the memory device, the controller being operable to generate a first state of a bit associated with each data block written from the cache into the memory device, the controller being operable to update the state to a second state opposite the first state for each bit associated with each data block read out of the memory device into the cache;
• wherein in response to the miss signal, the controller is operable to check the state of the bit associated with the data block addressable by the received address.

A cache memory controller comprising:

• a write buffer to store one or more blocks of data;
• a marker generator coupled to the write buffer to receive the one or more blocks of data, the marker generator to generate and append a marker bit to each block of data received from the write buffer;
• an interface controller coupled to the marker generator to receive each block of data with the appended marker bit, the interface controller for writing and reading blocks of data with the appended marker bit into and out of a memory device;
• and
• a marker checker coupled to the interface controller to receive a block of data with its respective appended marker bit read out from the memory device associated with a received address, the marker checker to check a state of the marker bit against an expected state of the marker bit to detect a false miss generated by a content addressable memory.