Closed-loop high-speed channel equalizer adaptation
AssigneeTexas Instruments Incorporated
InventorsRoland Sperlich, Huanzhang Huang, Charles M. Branch
Life of this patent
Estimating the term…
Abstract
A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an equalized data signal. A log detector circuit (300) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit (332) receives the power signal and produces a select signal. A first selection circuit (336) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.
Claims20
A circuit comprising:
- an input lead configured to receive a data signal;
- an equalizer circuit coupled with the input lead to receive the data signal, the equalizer circuit configured to equalize the data signal based on a correction signal;
- an equalization filter coupled with the equalizer circuit to receive the equalized data signal, the equalization filter configured to generate the correction signal based on a signal attenuation of the equalized data signal;
- and
- a regulation circuit coupled with the input lead to receive the data signal, and coupled with the equalization filter to receive the correction signal, the regulation circuit configured to selectively deliver the correction signal from the equalization filter to the equalizer circuit based on a power level of the data signal.
A circuit comprising:
- an equalizer circuit configured to receive a data signal, the equalizer circuit configured to equalize the data signal based on a correction signal;
- an first filter coupled with the equalizer circuit to receive the equalized data signal, the first filter configured to generate a first correction signal based on a first signal attenuation of the equalized data signal;
- an amplifier circuit coupled with the equalizer circuit to receive the equalized data signal, the amplifier circuit configured to amplify the equalized data signal;
- and
- an second filter coupled with the amplifier circuit to receive the amplified equalized data signal, the second filter configured to generate a second correction signal based on a second signal attenuation of the amplified equalized data signal;
- and
- a regulation circuit coupled with the first and second filters, the regulation circuit configured to generate the correction signal by selecting the first correction signal and the second correction signal based on a power level of the data signal.
A circuit comprising:
- an equalizer circuit configured to receive a data signal, the equalizer circuit configured to equalize the data signal based on a first correction signal;
- an first filter coupled with the equalizer circuit to receive the equalized data signal, the first filter configured to generate the first correction signal based on a first signal attenuation of the equalized data signal;
- an amplifier circuit coupled with the equalizer circuit to receive the equalized data signal, the amplifier circuit configured to amplify the equalized data signal based on a second correction signal;
- and
- an second filter coupled with the amplifier circuit to receive the amplified equalized data signal, the second filter configured to generate the second correction signal based on a second signal attenuation of the amplified equalized data signal;
- and
- a regulation circuit coupled with the first and second filters, the regulation circuit configured to selectively deliver the first correction signal to the equalizer circuit and selectively deliver the second correction signal to the amplifier circuit based on a power level of the data signal.
Dependencies are inferred from the claim text.