Noise shaped interpolator and decimator apparatus and method
AssigneeSTMicroelectronics S.r.l.
InventorsSteven R. Norsworthy, Jason Rupert Redgrave
Life of this patent
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Abstract
An interpolator or decimator includes an elastic storage element in the signal path between first and second clock domains. The elastic element may, for example, be a FIFO which advantageously allows short term variation in sample clocks to be absorbed. A feedback mechanism controls a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.
Claims22
A method for fractional-N interpolation or decimation, comprising:
- generating an error signal related to a difference between a first clock domain and a second clock domain;
- filtering the error signal;
- modulating the filtered error signal;
- generating a clock period signal based at least in part on the modulated filtered signal;
- and
- asynchronously clocking data out of or into an elastic storage element disposed between the first and second clock domains based at least in part on the clock period signal.
A fractional-N interpolation or decimation circuit, comprising:
- an elastic storage element disposed between a first clock domain and a second clock domain;
- a differencing circuit configured to generate an error signal related to a difference between the first and second clock domains;
- a filter circuit configured to filter the error signal;
- a modulator circuit configured to modulate the filtered error signal;
- and
- a counter circuit configured to generate a clock period signal based at least in part on the modulated filtered signal;
- wherein the clock period signal is applied to control asynchronously clocking data out of or into the elastic storage element.
A method, comprising:
- clocking data into an elastic buffer in accordance with a first clock domain;
- generating an error signal related to a difference between the first clock domain and a second clock domain;
- filtering the error signal;
- modulating the filtered error signal;
- generating a clock period signal based at least in part on the modulated filtered signal;
- and
- reading data from the elastic buffer based at least in part on the clock period signal.
A method, comprising:
- clocking data out of an elastic buffer in accordance with a first clock domain;
- generating an error signal related to a difference between the first clock domain and a second clock domain;
- filtering the error signal;
- modulating the filtered error signal;
- generating a clock period signal based at least in part on the modulated filtered signal;
- and
- writing data into the elastic buffer based at least in part on the clock period signal.
Dependencies are inferred from the claim text.