Multilayer circuit board and method for manufacturing the same
AssigneeTong Hsing Electronic Industries, Ltd.
InventorsChien-Cheng WEI, Ta-Hsiang CHIANG
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Abstract
A method for manufacturing a multilayer circuit board includes: forming a first patterned conductive layer on a ceramic substrate, the first patterned conductive layer having a first circuit pattern and a first submount pattern; forming a second patterned conductive layer on the first patterned conductive layer, the second patterned conductive layer having a second circuit pattern and a second submount pattern; forming an insulating layer on the ceramic substrate; and forming a third patterned conductive layer on the insulating layer. The third patterned conductive layer having a third circuit pattern and a third submount pattern. The first, second and third submount patterns are stacked one above another.
Claims13
A method for manufacturing a multilayer circuit board having a submount structure for mounting and heat dissipation of at least one semiconductor chip, comprising:
- providing a ceramic substrate;
- forming a first patterned conductive layer that is stacked on the ceramic substrate along a stacking direction, the first patterned conductive layer having a first circuit pattern and a first submount pattern;
- forming a second patterned conductive layer that is stacked on the first patterned conductive layer, the second patterned conductive layer having a second circuit pattern which is connected to the first circuit pattern, and a second submount pattern which is connected to and at least partially overlaps the first submount pattern along the stacking direction;
- forming an insulating layer on the ceramic substrate, such that the insulating layer is disposed among the first and second circuit patterns and the first and second submount patterns and that a top surface of the second patterned conductive layer is exposed from the insulating layer;
- and
- forming a third patterned conductive layer that is stacked on the insulating layer and the top surface of the second patterned conductive layer, the third patterned conductive layer having a third circuit pattern which is connected to the second circuit pattern, and a third submount pattern which is connected to and at least partially overlaps the second submount pattern along the stacking direction;
- wherein the second circuit pattern has a plurality of interconnections interconnecting the first circuit pattern and the third circuit pattern;
- and
- wherein the submount structure includes at least the first, second and third submount patterns.
A multilayer circuit board adapted for mounting and heat dissipation of at least one semiconductor chip and comprising:
- a ceramic substrate;
- a first patterned conductive layer that is stacked on said ceramic substrate along a stacking direction, said first patterned conductive layer having a first circuit pattern and a first submount pattern;
- a second patterned conductive layer that is stacked on said first patterned conductive layer, said second patterned conductive layer having a second circuit pattern which is connected to said first circuit pattern, and a second submount pattern which is connected to and at least partially overlaps said first submount pattern along the stacking direction;
- an insulating layer stacked on said ceramic substrate and disposed among said first and second circuit patterns and said first and second submount patterns, such that a top surface of said second patterned conductive layer is exposed from said insulating layer;
- and
- a third patterned conductive layer that is stacked on said insulating layer and said top surface of said second patterned conductive layer, said third patterned conductive layer having a third circuit pattern which is connected to said second circuit pattern, and a third submount pattern which is connected to and at least partially overlaps said second submount pattern along the stacking direction and which is adapted for mounting of the semiconductor chip thereon;
- wherein said second circuit pattern has a plurality of interconnections interconnecting said first circuit pattern and said third circuit pattern.
Dependencies are inferred from the claim text.