Time-to-digital converter, all digital phase locked loop circuit, and method

A time-to-digital converter, comprising:

• a phase interpolation circuit and a time-to-digital conversion circuit connected to the phase interpolation circuit, wherein
• the phase interpolation circuit is configured to:
• receive a first reference clock signal and a second reference clock signal, wherein a phase of the first reference clock signal is prior to a phase of the second reference clock signal;
• perform phase interpolation on the first reference clock signal and the second reference clock signal to generate a third reference clock signal;
• and output the third reference clock signal to the time-to-digital conversion circuit;
• and
• the time-to-digital conversion circuit is configured to:
• receive the third reference clock signal and a fourth clock signal, wherein a phase difference between the third reference clock signal and the fourth clock signal is less than a phase difference between the first reference clock signal and the fourth clock signal;
• measure the phase difference between the third reference clock signal and the fourth clock signal;
• and convert the measured phase difference into a digital signal for outputting.