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AssigneeQUALCOMM Incorporated
InventorsYu Song, Jan Christian Diffenderfer, Nan Chen, David Ian West, Paul Lawrence Viani
Estimating the term…
Systems and methods for recovering clock and data from a data input signal are disclosed that sample a plurality of clock phase signals with the data input signal to determine a timing relationship between the data input signal and the clock phase signals and use the determined to timing relationship to select one of the clock phase signals to use for sampling the data input signal to produce recovered data. The CDR can include a glitch suppression module to suppress glitches on the clock output signal that could be caused by large instantaneous jitter on the data input signal. A clock and data recovery circuit (CDR) using these methods can quickly lock to a new data input signal and can reliably receive data when there is large instantaneous timing jitter on the data input signal.
A circuit for recovering clock and data from a serial data input signal using clock phase signals, the data input signal containing a serial stream of data, the clock phase signals oscillating at a frequency that approximately matches a data rate of the data input signal, and the clock phase signals equally spaced in phase, the circuit comprising:
A method for recovering clock and data from a data input signal, the method comprising:
An apparatus for recovering clock and data from a data input signal, the apparatus including:
Dependencies are inferred from the claim text.