Graphene-based non-boolean logic circuits

A graphene-based pattern matching circuit comprising:

• a plurality of elementary cells coupled in series, each elementary cell comprising:
• a first G-FET having a first back-gate that is a first input;
• a second G-FET having a second back-gate that is a second input;
• and
• a third G-FET having a current output coupled in series with an adjacent one of the plurality of elementary cells and a third back-gate that is coupled to top-gates of the first G-FET and the second G-FET.

An apparatus comprising:

• a dual-gate transistor having a negative differential resistance (NDR) region comprising:
• a back-gate;
• a zero-bandgap graphene layer disposed on the back-gate;
• a top-gate disposed on a portion of the zero-bandgap graphene layer;
• a source disposed on a portion of the zero-bandgap graphene layer adjacent to the top-gate;
• and
• a drain disposed on a portion of the zero-bandgap graphene layer adjacent to the top-gate and displaced from the source;
• and
• a dynamic bias controller adapted to simultaneously sweep a source-drain voltage and a top-gate voltage across a Dirac point to cause the dual-gate transistor to operate within the NDR region.