Multi-Bit Standard Cells For Consolidating Transistors With Selective Sourcing

A non-transitory, computer-readable medium storing computer-executable instructions for designing a standard cell, the instructions when executed by a processor cause the processor to execute a process comprising:

• identifying a first set of transistors, the first set of transistors functioning to source power or ground to circuits of the standard cell;
• determining and correlating a second set of transistors, the second set of transistors forming at least part of the first set of transistors, wherein each correlated group in the second set of transistors receives identical signals and provides a same sourcing;
• creating a third set of transistors, the third set of transistors being less than the second set of transistors;
• deleting the second set of transistors;
• and
• using a computer, connecting the third set of transistors to the circuits of the standard cell.

An electronic design automation (EDA) program to be executed by a computer and stored on a non-transitory computer-readable medium, the EDA program comprising instructions, the instructions when executed by a processor cause the processor to execute a process comprising:

• identifying a first set of transistors, the first set of transistors functioning to source power or ground to circuits of the standard cell;
• determining and correlating a second set of transistors, the second set of transistors forming at least part of the first set of transistors, wherein each correlated group in the second set of transistors receives identical signals and provides a same sourcing;
• creating a third set of transistors, the third set of transistors being less than the second set of transistors;
• deleting the second set of transistors;
• and
• using the processor, connecting the third set of transistors to the circuits of the standard cell.

A multi-bit flip-flop comprising:

• a control block;
• for each bit of the multi-bit flip-flop,
• an input block for receiving a data input signal and a scan input signal;
• a master latch coupled to an output of the input block;
• and
• a slave latch coupled to an output of the master latch,
• wherein the control block comprises:
• a first transistor set for receiving a clock signal and generating a buffered clock signal and an inverted clock signal, the first transistor set being operatively coupled to the input block, the master latch, and the slave latch;
• a second transistor set for receiving a scan enable signal and generating an inverted scan enable signal, the second transistor set being operatively coupled to the input block;
• a first transistor for receiving the scan enable signal, a source of the first transistor connected to a high voltage source, a drain of the first transistor operatively connected to the input block;
• a second transistor for receiving the inverted scan enable signal, a source of the second transistor connected to a high voltage source, a drain of the second transistor operatively connected to the input block;
• and
• a third transistor for receiving a reset signal, a source of the third transistor connected to a low voltage source, a drain of the third transistor operatively connected to the master latch and the slave latch.