Adding Decoupling Function for TAP Cells
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuo-Ji Chen, Li-Chun Tien
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Abstract
A circuit includes a tap cell. The tap cell includes a well region, a first well pickup region in the well region, a VDD power rail and a VSS power rail spaced apart from the VDD power rail. The tap cell also includes a first jog extending from the VDD power rail toward the VSS power rail and forming a continuous region with the VDD power rail. The tap cell further comprises a first capacitor including a first gate electrode line acting as a first capacitor plate, and the first well pickup region acting as a part of a second capacitor plate. A first one of the first and second capacitor plates is overlapped by and connected to the first jog, and a second one of the first and second capacitor plates is coupled to the VSS power rail.
Claims20
A circuit comprising:
- a tap cell comprising:
- a well region;
- a first well pickup region in the well region;
- a VDD power rail;
- a VSS power rail spaced apart from the VDD power rail;
- a first jog extending from the VDD power rail toward the VSS power rail, wherein the first jog forms a continuous region with the VDD power rail;
- and
- a first capacitor comprising a first gate electrode line acting as a first capacitor plate, and the first well pickup region acting as a part of a second capacitor plate, wherein a first one of the first and second capacitor plates is overlapped by and connected to the first jog, and a second one of the first and second capacitor plates is coupled to the VSS power rail.
A circuit comprising:
- a tap cell comprising:
- a VDD power rail;
- a VSS power rail;
- a first capacitor comprising:
- an n-well region;
- a first gate electrode over the n-well region and connected to the VSS power rail;
- and
- a first well pickup region in the n-well region and on a first side of the first gate electrode, wherein the first well pickup region is connected to the VDD power rail;
- and
- a second capacitor comprising:
- a p-well region;
- a second gate electrode over the p-well region and connected to the VDD power rail, wherein each of the first and the second gate electrodes comprises portions overlapped by both the VDD power rail and the VSS power rail;
- and
- a second well pickup region in the p-well region and on a first side of the second gate electrode, wherein the second well pickup regions are connected to the VSS power rail.
A circuit comprising:
- a VDD power rail;
- a VSS power rail spaced apart from the VDD power rail;
- a first gate electrode forming a first capacitor plate of a first capacitor;
- an n-well pickup region forming a part of a second capacitor plate of the first capacitor;
- a second gate electrode parallel to the first gate electrode, wherein the second gate electrode forms a first capacitor plate of a second capacitor;
- a p-well pickup region forming a part of a second capacitor plate of the second capacitor;
- a first jog extending from the VDD power rail toward the VSS power rail, wherein the first jog overlaps the first gate electrode and the second gate electrode;
- a second jog extending from the VSS power rail toward the VDD power rail, wherein the second jog overlaps the first gate electrode and the second gate electrode;
- a first contact plug interconnecting the first jog and the second gate electrode;
- and
- a second contact plug interconnecting the second jog and the first gate electrode.
Dependencies are inferred from the claim text.