Self-aligned structures and methods for asymmetric gan transistors & enhancement mode operation

A method of forming an asymmetric high electron mobility transistor (HEMT), the method comprising:

• depositing a sacrificial material over a substrate comprising a group III-N channel layer;
• etching at least one trench to form a mandrel of the sacrificial material spaced apart by a first length and a second length, different from the first, from peripheral regions of the sacrificial material;
• conformally depositing a dielectric liner into the at least one trench and over the mandrel;
• depositing a bulk dielectric over the dielectric liner to fill the at least one trench;
• etching through the bulk dielectric and dielectric liner to expose the peripheral regions of the sacrificial material;
• etching the peripheral regions of the sacrificial material selectively to the dielectric liner to expose a semiconductor channel layer disposed at the periphery of the at least one trench;
• forming semiconductor source and drain regions in contact with the exposed semiconductor channel layer;
• etching through the bulk dielectric and dielectric liner to expose the mandrel;
• and replacing the mandrel with a gate stack.