Gallium nitride power devices using island topography

A nitride semiconductor device comprising:

• a substrate;
• a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate;
• a plurality of source island electrodes and a plurality of drain island electrodes of a multi-island transistor formed on the nitride semiconductor layer, the source island electrodes and drain island electrodes being spaced apart from each other and arranged as an array with alternating source island electrodes and drain island electrodes along at least two different axial directions to produce two-dimensional active regions in a device area of the nitride semiconductor layer;
• a plurality of gate strip electrodes formed on the nitride semiconductor layer in active regions between adjacent source island electrodes and drain island electrodes, an overlying low resistance gate interconnect running between the source island electrodes and drain island electrodes, the plurality of gate electrodes being interconnected to the low resistance gate interconnect by gate interconnections at interstices defined by adjacent vertices of the source island electrodes and the drain island electrodes;
• each of the plurality of source island electrodes having a respective individual source contact area (pad) comprising a bump, ball or post connection formed thereon;
• each of the plurality of drain island electrodes having a respective individual drain contact area (pad) comprising a bump, ball or post connection formed thereon;
• the low resistance gate interconnect being connected to a plurality of gate pads;
• and
• wherein, in defective active regions, individual gate strip electrodes are selectively disconnected from the gate interconnect by absence or removal of respective gate interconnections thereto.

A semiconductor device comprising:

• a substrate;
• a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate;
• a metallization layer formed on the nitride semiconductor layer defining a plurality of first island electrodes and a plurality of second island electrodes spaced apart from each other and arranged as an array with alternating first island electrodes and second island electrodes along at least two orthogonal directions to produce two- dimensional active regions in areas of the nitride semiconductor layer, with
• at least one side of each first island electrode opposite a side of an adjacent second island electrode;
• at least one side of each second island electrode opposite a side of an adjacent first island electrode;
• the first island electrodes and second island electrodes serving, respectively, as source island electrodes and drain island electrodes of a multi-island transistor, or, respectively, as cathode island electrodes and anode island electrodes of a multi-island diode;
• an overlying interconnect structure comprising one or more metallization layers and intervening insulating layers;
• the one or more metallization layers defining a plurality of first common electrodes and a plurality of second common electrodes, the first common electrodes and the second common electrodes being arranged as a second array with alternating first common electrodes and second common electrodes, the second array of first and second common electrodes overlying the array of the first and second island electrodes;
• each first common electrode being interconnected to a set of said first island electrodes by said one or more metallization layers and conductive vias;
• and
• each second common electrode being interconnected to a set of said second island electrodes by said one or more metallization layers and conductive vias;
• each of the first common electrodes providing an external first connection formed thereon comprising a ball, bump or post connection, and
• each of the second common electrodes comprises an external first connection formed thereon comprising a ball, bump or post connection.

A nitride semiconductor device comprising:

• a substrate;
• a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate;
• a plurality of source, drain and gate electrodes of a multi-island transistor formed on the nitride semiconductor layer, the plurality of source, drain and gate electrodes comprising concentric electrode islands of decreasing size and arranged as repeated square shaped concentric tracks of ohmic and Schottky contacts, every two ohmic contacts having a Schottky contact in between, a plurality of source concentric island electrodes and a plurality of drain concentric island electrodes being formed from said ohmic concentric tracks, the gate electrodes in between the source and drain concentric electrodes being formed from said Schottky concentric tracks, the source and drain concentric electrodes thereby being alternately arranged such that each source island electrode is adjacent to a drain island electrode with a gate electrode in between;
• an overlying dielectric isolation layer with an array of a plurality of overlying square shaped source metal pads and drain metal pads formed thereon, the source and drain metal pads being arranged alternately with each source metal pad adjacent a drain metal pad, the corners of each adjacent four metal pads being placed over a set of square shaped concentric tracks of source and drain concentric island electrodes;
• source concentric island electrodes being connected to a respective overlying source metal pad by conductive vias;
• drain concentric island electrodes being connected to a respective overlying drain metal pad by conductive vias;
• and
• a gate connection point located at the center of each set of concentric tracks and in spaces defined between adjacent corners of the source and drain metal pads.