Integrative resistive memory in backend metal layers

A method for forming a resistive memory cell, comprising:

• providing a semiconductor substrate having a plurality of complementary metal oxide semiconductor (CMOS) devices formed thereon, and having a plurality of exposed copper conductor contact regions;
• forming a blocking layer over the semiconductor substrate and copper conductor contact regions;
• forming a plurality of bottom electrodes within the blocking layer and in electrical contact with respective ones of at least a subset of the copper conductor contact regions;
• disposing a set of resistive memory cell layers above the blocking layer, comprising:
• disposing a resistive switching material above and in electrical contact with the plurality of bottom electrodes, and
• disposing an active metal material above and in electrical contact with the resistive switching material;
• disposing an etch stop layer including discrete etch stop segments over portions of the active metal material;
• etching the set of resistive memory cell layers between the discrete etch stop segments to form a plurality of resistive memory structures;
• depositing a first dielectric layer above and between the plurality of resistive memory structures;
• etching the first dielectric layer to expose the etch stop layer of the plurality of resistive memory structures;
• depositing a second dielectric layer above at least a portion of the first dielectric layer and above the etch stop layer of the plurality of resistive memory structures;
• forming and patterning a mask layer above discrete mask portions of the second dielectric layer;
• etching at least a portion of the second dielectric layer in response to the mask layer to form a plurality of contact vias that respectively expose at least a portion of the discrete etch stop segments of the plurality of resistive memory structures;
• and
• forming a copper metal layer within the plurality of contact vias above and respectively in electrical contact with the portion of the discrete etch stop segments of the plurality of resistive memory structures.

A method of forming a device including embedded resistive memory, comprising:

• providing a substrate having a plurality of CMOS devices formed thereon;
• forming a first copper metal layer over the substrate and comprising a plurality of copper contact pads;
• forming a plurality of resistive memory devices over a portion of surface area of the substrate and in contact with respective ones of a corresponding subset of the plurality of copper contact pads within the portion of the surface area, wherein the plurality of resistive memory devices are formed using two, three or four photo-resist mask layers and further wherein the plurality of resistive memory devices include respective ones of a set of first memory contact regions;
• forming a second copper metal layer above the plurality of resistive memory devices and in electrical contact with the set of first memory contact regions.