Semiconductor device including gate channel having adjusted threshold voltage
AssigneeInternational Business Machines Corporation
InventorsPranita Kerber, Qiqing C. Ouyang, Alexander Reznicek
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes at least one first semiconductor fin formed on an nFET region of a semiconductor device and at least one second semiconductor fin formed on a pFET region. The at least one first semiconductor fin has an nFET channel region interposed between a pair of nFET source/drain regions. The at least one second semiconductor fin has a pFET channel region interposed between a pair of pFET source/drain regions. The an epitaxial liner is formed on only the pFET channel region of the at least one second semiconductor fin such that a first threshold voltage of the nFET channel region is different than a second threshold voltage of the pFET channel.
Claims10
-11. (canceled)
A semiconductor device comprising:
- a semiconductor substrate including an nFET portion and a pFET portion separately located from the nFET portion;
- at least one first semiconductor fin formed on the nFET portion, the at least one first semiconductor fin having an nFET channel region interposed between a pair of nFET source/drain regions;
- and
- at least one second semiconductor fin formed on the pFET portion, the at least one second semiconductor fin having a pFET channel region interposed between a pair of pFET source/drain regions, pFET channel region including an etched portion of the at least one second semiconductor fin, and wherein the etched portion has a first thickness that is less than a second thickness of the at least one first semiconductor fin;
- and
- an epitaxial liner formed only on the pFET channel region such that a first threshold voltage of the nFET channel region is different than a second threshold voltage of the pFET channel region
- wherein the epitaxial liner is formed on the etched portion, the combination of the etched portion and the epitaxial liner defining a third thickness that is equal to the second thickness of the at least one first semiconductor fin.
(canceled)
(canceled)
Dependencies are inferred from the claim text.