US 2015/0318296 A1 · NON-VOLATILE MEMORY DEVICES WITH VERTICALLY INTEGRATED CAPACITOR ELECTRODES

Abstract

Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity. The device includes a substrate having a cell region and a peripheral circuit region, a memory cell string including a plurality of vertical memory cells formed in the cell region and channel holes formed to penetrate the vertical memory cells in a first direction vertical to the substrate, an insulating layer formed in the peripheral circuit region on the substrates at substantially the same level as an upper surface of the memory cell string, and a plurality of capacitor electrodes formed on the peripheral circuit region to penetrate at least a portion of the insulating layer in the first direction, the plurality of capacitor electrodes extending parallel to the channel holes. The plurality of capacitor electrodes are spaced apart from one another in a second direction parallel to the substrate, and the insulating layer is interposed between a pair of adjacent capacitor electrodes from among the plurality of capacitor electrodes.

Claims20

Dependent claims

A nonvolatile memory device, comprising:

a plurality of spaced-apart strings of vertically arranged nonvolatile memory cells on a memory cell region of a substrate;
channel regions vertically extending the plurality of spaced-apart strings;
an electrically insulating layer on a peripheral circuit region of the substrate, which extends adjacent the memory cell region;
and
a plurality of spaced-apart first capacitor electrodes on the peripheral circuit region, said first capacitor electrodes extending vertically and at least partially through said electrically insulating layer in a direction parallel to the channel regions in said plurality of spaced-apart strings of vertically arranged nonvolatile memory cells.

2 more elements

A non-volatile memory device comprising:

a substrate having a cell region and a peripheral circuit region;
a memory cell string including a plurality of memory cells stacked in the cell region on the substrate;
a lower insulating layer formed in the peripheral circuit region on the substrate;
an upper insulating layer formed on the lower insulating layer and having an upper surface disposed at substantially the same level as an upper surface of the memory cell string;
and
a plurality of vertical capacitors formed in via holes penetrating the upper insulating layer in a vertical direction to the substrate,
wherein each of the plurality of vertical capacitors comprises:
a first capacitor electrode formed along an inner wall of the via hole;
a second capacitor electrode surrounded with the first capacitor electrode in the via hole to fill the via hole;
and
a capacitor insulating layer interposed between the first capacitor electrode and the second capacitor electrode,
wherein the plurality of vertical capacitors are formed a sufficiently close distance apart from one another and extend parallel to one another such that charges are accumulated in the upper insulating layer interposed between a pair of adjacent vertical capacitors from among the plurality of vertical capacitors.

9 more elements

Dependencies are inferred from the claim text.

Non-volatile memory devices with vertically integrated capacitor electrodes

Life of this patent

Non-volatile memory devices with vertically integrated capacitor electrodes

Life of this patent

Abstract

Claims20