Method of Forming an Embedded Memory Device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Wei Ting, Kuo-Ching Huang, Chih-Yang Pai
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Abstract
The present disclosure describes a method of forming a memory device. The method includes receiving a wafer substrate, forming a poly stack pattern on the wafer substrate, performing an ion implantation process to form a source and a drain in the wafer substrate, forming a memory gate and a control gate in the defined poly stack pattern, and forming a control gate in the control poly stack pattern. Forming the memory gate further includes performing a memory gate recess to bury the memory gate in an oxide layer.
Claims20
A memory structure, the structure comprising:
- a wafer substrate;
- a source formed in the wafer substrate;
- a drain formed in the wafer substrate;
- and
- a poly stack pattern disposed over the source at one end of the poly stack pattern and over the drain at another end of the poly stack pattern, wherein the poly stack pattern includes a memory gate over the source and a control gate over the drain.
A device comprising:
- a memory gate region disposed over a semiconductor substrate, the memory gate region including:
- an interfacial layer disposed over the semiconductor substrate in the memory gate region;
- a memory gate disposed over the interfacial layer;
- and
- a spacer disposed along a sidewall of memory gate and disposed between the memory gate and the interfacial layer;
- a control gate region disposed over the semiconductor substrate, the control gate region including:
- the interfacial layer disposed over the semiconductor substrate in the control gate region;
- a high-k dielectric layer disposed over the interfacial layer in the control gate region;
- a metal nitride layer disposed over the high-k dielectric layer;
- and
- a control gate disposed over the metal nitride layer.
A device comprising:
- a memory gate region disposed over a semiconductor substrate, the memory gate region including:
- an interfacial layer disposed over the semiconductor substrate in the memory gate region;
- a spacer layer having a u-shaped profile defining a recess, the spacer layer disposed directly on the interfacial layer;
- and
- a memory gate disposed within the recess;
- and
- a control gate region disposed over the semiconductor substrate, the control gate region including:
- the interfacial layer disposed over the semiconductor substrate in the control gate region;
- a high-k dielectric layer disposed directly on the interfacial layer in the control gate region;
- a metal nitride layer disposed directly on the high-k dielectric layer;
- and
- a control gate disposed directly on the metal nitride layer.
Dependencies are inferred from the claim text.