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US 2015/0318286 A1Published application
Semiconductor device and method of manufacturing the same
AssigneesNan WU, PS5 Luxco S.a.r.l.
InventorNoriyasu Ikeda
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Abstract
This semiconductor device comprises: a bit line that is arranged in a memory cell region on a semiconductor substrate; and a gate electrode of a transistor for a peripheral circuit, which is arranged in a peripheral circuit region on the semiconductor substrate. The lateral surface of the gate electrode is provided with a plurality of side wall insulating films, while the lateral surface of the bit line is provided with a single side wall insulating film.
Claims6
A semiconductor device comprising:
- a memory cell region;
- a peripheral circuit region on a semiconductor substrate;
- bit lines arranged on said semiconductor substrate in said memory cell region;
- gate electrodes of transistors for peripheral circuits arranged on said semiconductor substrate in said peripheral circuit region;
- a plurality of sidewall insulating films on the lateral surfaces of said gate electrodes and
- a single-layer sidewall insulating film arranged on the lateral surfaces of said bit lines.
3 more elements
A method of manufacturing a DRAM semiconductor device, the method comprising:
- simultaneously forming a plurality of bit lines in a memory cell region on a semiconductor substrate and gate electrodes of transistors for peripheral circuits in a peripheral circuit region;
- forming, by etching back, a first liner film using a first insulating film only in a portion contacting the lateral surfaces of said bit lines and the lateral surfaces of said gate electrodes, after deposition of said first insulating film so as to cover said bit lines and said gate electrodes;
- and
- forming, by etching back, a spacing film using a second insulating film only in a portion contacting the lateral surfaces of said bit lines and said gate electrodes covered by said first liner film, after deposition, to a prescribed thickness, of said second insulating film, which is made of a different material from said first insulating film, in a region including the surfaces of said bit lines and said gate electrodes and the lateral surfaces covered by said first liner film;
- wherein the interval between said plurality of bit lines is set so that, when said spacing film is formed to said prescribed thickness, the space between adjacent bit lines is buried by said first liner film and said spacing film formed thereon;
- and
- after the step of forming said spacing film, deposition of a third insulating film made of the same material as said first insulating film in a region including the surfaces of said bit lines and said gate electrodes and the lateral surfaces covered by said first liner film and said spacing film, and then forming, by etching back, a second liner film using said third insulating film, only in a portion contacting the lateral surfaces of said gate electrodes covered by said spacing film and said first liner film.
4 more elements
Dependencies are inferred from the claim text.