Self aligned structure and method for high-k metal gate work function tuning

A method for fabricating a semiconductor device, the method comprising:

• forming a shallow trench isolation in a semiconductor substrate, wherein the shallow trench isolation has a first, second, and third portion, and the semiconductor substrate has a nFET region and a pFET region;
• depositing a high-k dielectric layer on the semiconductor substrate and shallow trench isolation;
• depositing a TiN layer on the high-k dielectric layer;
• depositing a polycrystalline silicon layer on the TiN layer;
• forming a block level litho layer on the polycrystalline silicon layer, wherein the block level litho layer is formed above the nFET region;
• removing the polycrystalline silicon layer above the pFET region, wherein the polycrystalline silicon layer above the nFET region has a sidewall;
• removing the block level litho layer;
• forming a first protective layer on the sidewall of the polycrystalline silicon layer above the nFET region, wherein the protective layer is formed above the second portion of the shallow trench isolation;
• depositing a fill layer on the TiN layer above the pFET region;
• removing the first protective layer;
• cutting the TiN layer and the high-k dielectric layer so that the second portion of the shallow trench isolation is exposed;
• depositing a second protective layer on the second portion of the shallow trench isolation;
• removing the fill layer;
• removing the TiN layer above the pFET region;
• treating the high-k dielectric layer above the pFET region with a work function tuning process;
• removing the polycrystalline silicon layer and the TiN layer above the nFET region;
• and
• depositing a metal layer on the high-k dielectric layer and the second protective layer.