Semiconductor Package Devices

A semiconductor package device, comprising:

• a lower package comprising a lower substrate and a lower semiconductor chip on the lower substrate;
• an upper package on the lower package, wherein the upper package comprises an upper substrate and an upper semiconductor chip on the upper substrate, and wherein the upper substrate comprises a protruding part overlying the lower semiconductor chip and a connection part having a bottom surface that is lower than a bottom surface of the protruding part and being disposed around the protruding part;
• a heat dissipation part between the lower semiconductor chip and the protruding part of the upper substrate, the heat dissipation part comprising a TIM and a metal heat slug;
• and
• a package connection pattern electrically connecting the lower package and the upper package.

A semiconductor package device, comprising:

• a lower package comprising a lower substrate, a lower semiconductor chip on the lower substrate and a lower mold part covering a sidewall of the lower semiconductor chip;
• an upper package on the lower package, wherein the upper package comprises an upper substrate and an upper semiconductor chip on the upper substrate, and wherein the upper substrate comprises a protruding part that protrudes upward, a connection part that is positioned at a lower level than a level of the protruding part and a slope part between the protruding part and the connection part;
• a heat dissipation part in a space between the lower semiconductor chip and the protruding part of the upper substrate, the heat dissipation part comprising a thermal interface material (TIM);
• and
• a package connection pattern electrically connecting the lower package and the upper package.