3d stacked-chip package
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen-Hua Yu, Ming-Fa Chen, Wen-Sen Lu, Wen-Chih Chiou, Wen-Ching Tsai
Life of this patent
Estimating the term…
Loading patent…
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen-Hua Yu, Ming-Fa Chen, Wen-Sen Lu, Wen-Chih Chiou, Wen-Ching Tsai
Estimating the term…
Disclosed herein is a package comprising a first die having a first redistribution layer (RDL) disposed on a first side of a first substrate and a second die having a second RDL disposed on a first side of a second substrate, with the first RDL bonded to the second RDL. A third die having a third RDL is disposed on a first side of a third substrate, the third die mounted over the second die, with the second die disposed between the first die and the third die. First vias extend through, and are electrically isolated from, the second substrate, with the first vias each contacting a conductive element in the first RDL or the second RDL. Second vias extend through, and are electrically isolated from, the third substrate, with the second vias each contacting a conductive element in the third RDL or one of the first vias.
A package, comprising:
A package, comprising:
A method, comprising:
Dependencies are inferred from the claim text.