Packaging substrate and semiconductor package having the same

A semiconductor package, comprising:

• a laminated body;
• first, second and third conductive pads formed on a surface of the laminated body;
• a plurality of conductive bumps mounted on the first, second and third conductive pads, respectively, wherein the conductive bumps have a maximum width greater than or equal to the width of the first, second and third conductive pads, the third conductive pad being positioned outside of an area between projections of the conductive bumps on the first and second conductive pads on the surface of the laminated body;
• first, second and third conductive vias formed in the laminated body and electrically connected to the first, second and third conductive pads, respectively;
• first, second and third internal conductive traces formed in the laminated body and electrically connected to the first, second and third conductive vias, respectively;
• and
• at least a chip disposed on the conductive bumps.

A packaging substrate, comprising:

• a laminated body;
• first, second and third conductive pads formed on a surface of the laminated body so as for conductive bumps to be respectively mounted thereon, wherein the first, second and third conductive pads have a width greater than the maximum width of the conductive bumps and less than two times the maximum width of the conductive bumps, the third conductive pad being positioned outside of an area between projections of the conductive bumps on the first and second conductive pads on the surface of the laminated body;
• first, second and third conductive vias formed in the laminated body and electrically connected to the first, second and third conductive pads, respectively;
• and
• first, second and third internal conductive traces formed in the laminated body and electrically connected to the first, second and third conductive vias, respectively.

A semiconductor package, comprising:

• a laminated body;
• first, second and third conductive pads formed on a surface of the laminated body;
• a plurality of conductive bumps mounted on the first, second and third conductive pads, respectively, wherein the first, second and third conductive pads have a width greater than the maximum width of the conductive bumps and less than two times the maximum width of the conductive bumps, the third conductive pad being positioned outside of an area between projections of the conductive bumps on the first and second conductive pads on the surface of the laminated body;
• first, second and third conductive vias formed in the laminated body and electrically connected to the first, second and third conductive pads, respectively;
• first, second and third internal conductive traces formed in the laminated body and electrically connected to the first, second and third conductive vias, respectively;
• and
• at least a chip disposed on the conductive bumps.