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US 2015/0318252 A1Published application
Semiconductor Package and Method of Manufacturing the Same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWen-Hsiung Lu, Ming-Da Cheng, Yi-Wen Wu, Yu-Peng Tsai, Chia-Wei Tu, Chung-Shi Liu
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Abstract
A semiconductor package includes a semiconductor substrate, a contact pad overlying the semiconductor substrate, an interconnect layer overlying the contact pad, a passivation layer formed between the contact pad and the interconnect layer, a bump overlying the interconnect layer, and a protection layer overlying the interconnect layer and the passivation layer and covering a lower portion of the bump. The protection layer includes a curved surface region.
Claims20
A structure comprising:
- a contact pad over a substrate;
- a passivation layer over the substrate;
- a first buffer layer over the passivation layer;
- a post-passivation interconnect extending over the first buffer layer and extending through an opening in the first buffer layer to contact the contact pad;
- a solder bump over and coupled to the post-passivation interconnect, a portion of the solder bump extending into the opening in the first buffer layer;
- and
- a protection layer over the post-passivation interconnect and the first buffer layer, the protection layer surrounding a lower portion of the solder bump.
4 more elements
A method comprising:
- forming a contact pad over a substrate;
- forming a passivation layer over the substrate;
- forming a first buffer layer over the passivation layer, the first buffer layer having a first opening exposing a portion of the contact pad;
- forming a post-passivation interconnect over the first buffer layer and in the first opening in the first buffer layer to contact the contact pad;
- forming a solder bump over and coupled to the post-passivation interconnect, a portion of the solder bump extending into the first opening in the first buffer layer;
- and
- forming a protection layer over the post-passivation interconnect and the first buffer layer, the protection layer surrounding a lower portion of the solder bump.
4 more elements
A method comprising:
- forming a first passivation layer over a substrate;
- forming a first opening through the first passivation layer to expose a conductive feature in the substrate;
- forming a contact pad over the first passivation layer and in the first opening to contact the conductive feature;
- forming a second passivation layer over the contact pad;
- forming a second opening through the second passivation layer to expose a portion of the contact pad;
- forming a first buffer layer over the second passivation layer and in the second opening;
- forming a third opening through the first buffer layer to expose a portion of the contact pad;
- forming a post-passivation interconnect over the first buffer layer and in the third opening to contact the contact pad;
- forming a solder bump over and coupled to the post-passivation interconnect, a portion of the solder bump extending into the third opening in the first buffer layer;
- and
- forming a protection layer over the post-passivation interconnect and the first buffer layer, the protection layer surrounding a lower portion of the solder bump.
8 more elements
Dependencies are inferred from the claim text.