Device packaging with substrates having embedded lines and metal defined pads
AssigneeIntel Corporation
InventorsMark S. HLAD, Islam A. SALAMA, Mihir K. ROY, Tao WU, Yueli LIU, Kyu Oh LEE
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Abstract
Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.
Claims14
A method of forming an integrated circuit (IC) package substrate, the method comprising:
- laminating a first dielectric layer over a first metal feature;
- laser drilling a via in the dielectric layer to expose the first metal feature;
- laser patterning a trace in the dielectric laterally displaced from the via;
- electrolytically plating a fill metal into the via and the trace;
- planarizing the fill metal to a top surface of the dielectric layer;
- laminating and patterning dry resist film to expose via without exposing the trace;
- plating a surface finish metal over the exposed via fill metal;
- removing the dry film resist;
- and
- exposing the dielectric layer between the via and the trace.
An integrated circuit (IC) package substrate, comprising:
- a first surface-level metal feature embedded in a surface-level dielectric layer with a top surface of a fill metal planar with a top surface of the surface-level dielectric;
- and
- a surface finish metal disposed over a top surface of the first surface level metal feature, the surface finish metal protruding beyond the top surface of the surface-level dielectric layer and having a different composition than the fill metal.
A package assembly, comprising:
- an integrated circuit (IC) chip with input/output (I/O) and power connection points;
- and
- a package substrate, comprising:
- a first surface-level metal feature comprising a fill metal embedded in a surface-level dielectric layer;
- and
- a surface finish metal disposed over a top surface of the fill metal, the surface finish metal protruding beyond a top surface of the surface-level dielectric layer, wherein the surface finish metal has a different composition than the fill metal, and wherein the surface finish metal is affixed to a first of the connection points by solder.
Dependencies are inferred from the claim text.